Toshiba has created 32 Gb the chip 3D NAND flash-memories

Toshiba has presented on the Symposium on the big integrated schemes (VLSI Circuits) 32-gigabitnyj chip NAND of flash-memory with multilevel cells (MLC), placed in vertical position. Such structure has a three-dimensional appearance and consequently it name 3D flash-memory.

32-gigabitnyj chip P-BiCS (Pipe-shaped Bit Cost Scalable) includes 16 levels of cells, each of which is capable to store 2 bits of the information. The chip is created on norms of 60-nanometer tehprotsessa and has the sizes 10,11 h 15,52 mm. The working surface of a cell on 1 bit makes 0,00082 mkm2, it is less, than at 32-nanometer of chips NAND of the flash-memory which manufacture will be already started this year.

File of cells 3D flash-memories

Chip P-BiCS is advanced variant BiCS — 3D-memories NAND flash which Toshiba developed since 2007 In BiCS the technology of the multilevel organisation of cells of memory is realised, it became possible for the account:

1. Serial packing of a film of an electrode of a shutter with a film dielektrika;

2. Groupings of cells so that between levels the through aperture was created;

3. Embeddings of the channel of polycrystalline silicon.

Such way of grouping of cells has two big advantages in comparison with I-sequence.

First, properties of an isolating film thus amplify, and ability of cells to keep data improves.

Data can be stored in 3D-memory throughout 10 years

In BiCS the isolating film which has been laid out on a wall on the one hand of the tunnel, is damaged in the course of work that leads to deterioration of remembering properties of the chip. Toshiba still in 2007 declared, that it managed to reduce damage at the expense of change of a material for a tunnel isolating film: instead of dioksida silicon, silicon nitride has been applied. However, the new material and has not provided sufficient level of remembering properties for 3D flash-memory.

Secondly, thanks to the improved work of a line of a source of the transistor there are operations of data reading/data recording BiCS, the chip to I-shaped sequence of the cells faster, the switching transistor (selection transistor) and a source line are located in the bottom part of sequence.

In P-BiCS where cells are organised in the U-shaped sequence, the switching transistor and a source line settle down in the top part of sequence. Thus, at consecutive connection of cells neither the switching transistor, nor a source line are not exposed to high-temperature influence (nearby 1000°C). As a result, the number of errors decreases at reading.

For a line of a source of the transistor it is possible to use metal materials, therefore speed of record at P-BiCS chips above in comparison with BiCS. In BiCS as a line of a source of the transistor it is used diffuzionnyiy a layer which tends to high resistance. High resistance of a line of a source of the transistor increases fluctuations of threshold pressure in a file of cells owing to what speed of record decreases.

Developers of chip P-BiCS are going to introduce mass production 3D flash-memories NAND in 2-3 years. The given technology will allow to make vyisokoemkie chips NAND of flash-memory without necessity of the further miniaturization tehnorm manufactures.