Dispersal it is simple: operative memory

We already told about how to disperse processors and video cards. One more component aloud enough influencing productivity of separately taken computer, – operative memory. Speeding up and thin adjustment of the mode of operation of the RAM allow to raise speed of the personal computer on the average on 5–10 %. If the similar gain is reached without any monetary investments and does not attract risks for stability of system – why not to try? However having started to prepare the given material, we have come to conclusions thatdescriptions actually dispersal process will be insufficiently. To understand, why and for what it is necessary to change certain options of work of modules, it is possible, only having penetrated into an essence of work of a subsystem of memory of the computer. Therefore in the first part of a material we will short consider the general principles of functioning of the RAM. In the second the basic advices which it is necessary to adhere a beginner overklokeram at dispersal of a subsystem of memory are resulted.

Main principles of functioning of operative memory are identical to modules of different types. The leading developer of standards of semi-conductor industry JEDEC grants possibility to each wishing to familiarise with the open documents devoted to these subjects. We will try to explain base concepts short.

So, operative memory is the matrix consisting of files, named as memory banks. They form so-called information pages. The memory bank reminds the table which each cell has co-ordinates on a vertical (Column) and horizontals (Row). Memory cells represent the condensers, capable to accumulate an electric charge. By means of special amplifiers analogue signals are transferred in digital which are formed in turn by data. Alarm chains of modules supply additional charge of condensers and a data recording/reading.

The algorithm of work of dynamic memory can be described such sequence:

1. The chip with which work (command Chip Select, CS) will be carried out gets out. The electric signal conducts activation of the chosen line (Row Activate Selection). Data get on amplifiers and can be schitanyi certain time. This operation in the English-speaking literature is called Activate.
2. Data are read out from the corresponding kolonki/register in it (operations Read/Write). The choice of columns is conducted by command CAS (Column Activate Selection).
3. While the line on which the signal is given, remains active, is possible schityvanie/zapis cells of memory corresponding to it.
4. At data reading – charges of condensers – their capacity is lost, additional charge or closing of a line with a data recording in a memory file (Precharge) therefore is required.
5. Condensers-cells lose in due course the capacity and require constant additional charge. This operation – Refresh – is executed regularly through separate intervals (64 ms) for every line file of memory.

On fulfilment of the operations occurring in operative memory, some time leaves. Also it is accepted to name it such familiar word «taymingi» (from English time). Hence, taymingi – the time intervals necessary for fulfilment of those or other operations, RAMS carried out in work.

The scheme taymingov, modules of memory indicated on stickers, includes only basic delay CL-tRCD-tRP-tRAS (CAS Latency, RAS to CAS Delay, RAS Precharge and Cycle Time (or Active to Precharge)). The others, in a smaller measure works of the RAM influencing speed, it is accepted to name all subtaymingami, additional or minor taymingami.

We result decoding of the basic delay arising at functioning of modules of memory:

CAS Latency (CL) – perhaps, the most important parametre. Defines minimum time between command giving on reading (CAS) and the data transfer beginning (reading delay).

RAS to CAS Delay (tRCD) defines time interval between giving of commands RAS and CAS. Designates number of the steps necessary for receipt of data in the amplifier.

RAS Precharge (tRP) – time leaving on a recharge of cells of memory after hours of bank.

Row Active Time (tRAS) – the time interval on which extent the bank remains opened and does not require a recharge.

Command Rate 1/2T (CR) – time necessary for decoding by the controller of commands and addresses. At significance 1T the command is distinguished for one step, at 2T – for two.

Bank Cycle Time (tRC, tRAS/tRC) – time of a complete step of access to memory bank, since opening and finishing closing. It is changed together with tRAS.

DRAM Idle Timer – an idle time of open information page for data reading from it.

Row to Column (Read/Write) (tRCD, tRCDWr, tRCDRd) directly it is connected with parametre RAS to CAS Delay (tRCD). It is calculated under the formula tRCD (Wr/Rd) = RAS to CAS Delay + Rd/Wr Command Delay. The second composed – the size noncontrollable, defines delay on data recording/data reading fulfilment

Perhaps, it is a base set taymingov, frequently accessible to change in BIOS parent payments. Decoding of other delay, as well as the detailed description of principles of work and definition of influence of those or other parametres on RAM functioning can be found in specifications already mentioned by us JEDEC, and also in opened datasheet manufacturers of sets of system logic.

The table of conformity of real, effective frequency of work and rating of different types of the RAM
Memory type Rating Real frequency
Memory works, MHz Effective frequency
Memory works
(DDR, Double Data Rate), MHz DDR PC 2100 133 266 PC 2700 167 333 PC 3200 200 400 ZS 3500 217 434 PC 4000 250 500 PC 4300 266 533 DDR2 PC2 4300 266 533 PC2 5400 333 667 PC2 6400 400 800 PC2 8000 500 1000 PC2 8500 533 1066 PC2 9600 600 1200 PC2 10 400 650 1300 DDR3 PC3 8500 533 1066 PC3 10 600 617,5 1333 PC3 11 000 687,5 1375 PC3 12 800 800 1600 PC3 13 000 812,5 1625 PC3 14 400 900 1800 PC3 15 000 933 1866 Let’s notice, that the numerical designation of a rating in this case according to specifications JEDEC indicates for the speed in millions transfers to second through one conclusion of data.
As to speed and symbols instead of effective frequency of work more correctly to say, that speed of data transfer twice more than clock frequency of the module (data are transmitted on two fronts of signals of the clock generator).

The basic taymingi memories

The similar formula of delay can be found out on stickers of modules of the RAM. In it the basic are presented only taymingi, in the greatest measure subsystems of memory influencing productivity.

To understand, that designate these four delay, and to begin with at least to remember names, – one of steps to successful dispersal. Data taymingi whenever possible it is necessary to lower to a minimum.

Explanation of one of taymingov tRP (Read to Precharge, RAS Precharge) by means of the typical scheme in datasheet from JEDEC. Decoding of signatures: CK and CK – clock signals of the data transfer, inverted one concerning other (Differential Clock); COMMAND – the commands acting on cells of memory; READ – reading operation; NOP – commands are absent; PRE – additional charge of condensers – memory cells; ACT – operation of activation of a line; ADDRESS – addressing of data to memory banks; DQS – the tyre of data (Data Strobe); DQ – the tyre of input-output of data (Data Bus: Input/Output); CL – CAS Latency in this case it is equal to two steps; DO n – data read-out since a line n. One step – the time interval necessary for return of signals of data transfer CK and CK in initial position, fixed during the certain moment.

The simplified block diagramme explaining bases of work of memory of standard DDR2. It is created for the purpose of demonstration of possible conditions of transistors and commands which supervise them. As you can see, to understand so "simple" scheme, one hour of studying of bases of work of the RAM is required not (we any more do not speak about understanding of all processes occurring in chips of memory).